A semiconductor fabrication technology, as the most rapidly developing technology in the 20th century, is gradually applied into the whole industry production. The semiconductor technology plays a huge role in a modern life. At the same time of pursuing excellent performance of a semiconductor electronic product such as a mobile phone and a computer, it is also desired that the product has a smaller volume, occupies a smaller space, and is more portable and more easily-operated. Therefore, under the
Moore's Law, the whole semiconductor industry is being aimed towards a high integration degree, a low power consumption and a high performance. As a feature size is gradually reduced, how to deal with an increasingly serious short channel effect and a series of accompanied deteriorations of device performance will become a key focus of the whole semiconductor industry in the future.
From a conventional planar field effect transistor to an ultra-thin bulk field effect transistor and then to a transistor of a multi-gate and surrounding-gate structure, in order to seek for a better gate control ability and to suppress the short channel effect and a drain-induced barrier lowering effect, there are emerging a lager number of semiconductor devices with new structures. Among them, a one-dimensional nanowire surrounding-gate structure field effect transistor gradually draws more and more attention due to an excellent gate control ability and an advantage in terms of mobility. If the one-dimensional nanowire surrounding-gate structure field effect transistor may be vertically arranged into an array by using a conventional semiconductor fabrication technology, the integration degree of a chip may be further increased, and a production cost may be greatly reduced. However, the conventional vertical silicon nanowire field effect transistor has a limitation. On one hand, since a size of a drain closes to a size of a channel, a large parasitic resistance may be caused and the speed and performance of the transistor may be adversely affected. Therefore, reducing the adverse influence of parasitic resistance by improving a process is a concern of the vertical silicon nanowire transistor. On the other hand, a difficulty in achieving the vertical silicon nanowire field effect transistor lies in a self-alignment of the source/drain and a gate. Due to a vertical structure, in the fabrication of the vertical silicon nanowire field effect transistor, the self-alignment can not be achieved by firstly defining a gate structure and then performing implantation for the source/drain as for a planar field effect transistor.